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PDF洗MD提示词 v5 实验测试 — PM0214样张6页

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- source/: PyMuPDF 提取的原始文本（p1/p2/p12/p13/p51/p52）
- output/: v5提示词处理后的Markdown结果
- output/imgs/: 封面占位符

Co-Authored-By: Claude <noreply@anthropic.com>
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hwd32
2026-06-10 08:20:04 +08:00
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output/00_目录.md
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| 章节号 | 标题 | 页码 |
|--------|------|------|
| 1 | About this document | 12 |
| 1.1 | Typographical conventions | 12 |
| 1.2 | List of abbreviations for registers | 12 |
| 1.3 | About the STM32 Cortex-M4 processor and core peripherals | 13 |
| 1.3.1 | System level interface | 14 |
| 1.3.2 | Integrated configurable debug | 14 |
| 1.3.3 | Cortex-M4 processor features and benefits summary | 15 |
| 1.3.4 | Cortex-M4 core peripherals | 16 |
| 2 | The Cortex-M4 processor | 17 |
| 2.1 | Programmers model | 17 |
| 2.1.1 | Processor mode and privilege levels for software execution | 17 |
| 2.1.2 | Stacks | 17 |
| 2.1.3 | Core registers | 18 |
| 2.1.4 | Exceptions and interrupts | 26 |
| 2.1.5 | Data types | 26 |
| 2.1.6 | The Cortex microcontroller software interface standard (CMSIS) | 26 |
| 2.2 | Memory model | 28 |
| 2.2.1 | Memory regions, types and attributes | 29 |
| 2.2.2 | Memory system ordering of memory accesses | 29 |
| 2.2.3 | Behavior of memory accesses | 30 |
| 2.2.4 | Software ordering of memory accesses | 31 |
| 2.2.5 | Bit-banding | 32 |
| 2.2.6 | Memory endianness | 34 |
| 2.2.7 | Synchronization primitives | 34 |
| 2.2.8 | Programming hints for the synchronization primitives | 36 |
| 2.3 | Exception model | 37 |
| 2.3.1 | Exception states | 37 |
| 2.3.2 | Exception types | 37 |
| 2.3.3 | Exception handlers | 39 |
| 2.3.4 | Vector table | 40 |
| 2.3.5 | Exception priorities | 41 |
| 2.3.6 | Interrupt priority grouping | 41 |
| 2.3.7 | Exception entry and return | 42 |
output/1.1_Typographical_conventions_p12.md
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来源：PM0214 Rev 10，Page 12
# 1 About this document
This document provides the information required for application and system-level software development. It does not provide information on debug components, features, or operation.
This material is for microcontroller software and hardware engineers, including those who have no experience of Arm products.
This document applies to Arm®(a)-based devices.
## 1.1 Typographical conventions
The typographical conventions used in this document are:
| Style | Indication |
|-------|------------|
| italic | Highlights important notes, introduces special terminology, denotes internal cross-references, and citations. |
| **bold** | Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate. |
| `monospace` | Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code. |
| `monospace` | Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name. |
| `monospace italic` | Denotes arguments to monospace text where the argument is to be replaced by a specific value. |
| `monospace bold` | Denotes language keywords when used outside example code. |
## 1.2 List of abbreviations for registers
The following abbreviations are used in register descriptions:
| Abbreviation | Meaning |
|--------------|---------|
| read/write (rw) | Software can read and write to these bits. |
| read-only (r) | Software can only read these bits. |
| write-only (w) | Software can only write to this bit. Reading the bit returns the reset value. |
| read/clear (rc_w1) | Software can read as well as clear this bit by writing 1. Writing '0' has no effect on the bit value. |
| read/clear (rc_w0) | Software can read as well as clear this bit by writing 0. Writing '1' has no effect on the bit value. |
| toggle (t) | Software can only toggle this bit by writing '1'. Writing '0' has no effect. |
| Reserved (Res.) | Reserved bit, must be kept at reset value. |
> 原始图片：imgs/page_12_*.png（无图则注明无图）
output/1.3_About_the_STM32_Cortex-M4_processor_and_core_peripherals_p13.md
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来源：PM0214 Rev 10，Page 13
## 1.3 About the STM32 Cortex-M4 processor and core peripherals
The Cortex-M4 processor is a high performance 32-bit processor designed for the microcontroller market. It offers significant benefits to developers, including:
- outstanding processing performance combined with fast interrupt handling
- enhanced system debug with extensive breakpoint and trace capabilities
- efficient processor core, system and memories
- ultra-low power consumption with integrated sleep modes
- platform security robustness, with integrated memory protection unit (MPU).
The Cortex-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including IEEE754-compliant single-precision floating-point computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division.
**Figure 1. STM32 Cortex-M4 implementation**
![图 1](imgs/page_13_fig_1.png)
> 原始图片：imgs/page_13_*.png
output/The_STM32_Cortex-M4_instruction_set_p51.md
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来源：PM0214 Rev 10，Page 51
# The STM32 Cortex-M4 instruction set
**Table 21. Cortex-M4 instructions (continued)**
| Mnemonic | Operands | Brief description | Flags | Page |
|----------|----------|-------------------|-------|------|
| AND, ANDS | {Rd,} Rn, Op2 | Logical AND | N,Z,C | 3.5.2 on page 85 |
| ASR, ASRS | Rd, Rm, <Rs\|#n> | Arithmetic shift right | N,Z,C | 3.5.3 on page 86 |
| B | label | Branch | — | 3.9.5 on page 142 |
| BFC | Rd, #lsb, #width | Bit field clear | — | 3.9.1 on page 139 |
| BFI | Rd, Rn, #lsb, #width | Bit field insert | — | 3.9.1 on page 139 |
| BIC, BICS | {Rd,} Rn, Op2 | Bit clear | N,Z,C | 3.5.2 on page 85 |
| BKPT | #imm | Breakpoint | — | 3.11.1 on page 181 |
| BL | label | Branch with link | — | 3.9.5 on page 142 |
| BLX | Rm | Branch indirect with link | — | 3.9.5 on page 142 |
| BX | Rm | Branch indirect | — | 3.9.5 on page 142 |
| CBNZ | Rn, label | Compare and branch if non zero | — | 3.9.6 on page 144 |
| CBZ | Rn, label | Compare and branch if zero | — | 3.9.6 on page 144 |
| CLREX | — | Clear exclusive | — | 3.4.9 on page 80 |
| CLZ | Rd, Rm | Count leading zeros | — | 3.5.4 on page 87 |
| CMN | Rn, Op2 | Compare negative | N,Z,C,V | 3.5.5 on page 88 |
| CMP | Rn, Op2 | Compare | N,Z,C,V | 3.5.5 on page 88 |
| CPSID | iflags | Change processor state, disable interrupts | — | 3.11.2 on page 182 |
| CPSIE | iflags | Change processor state, enable interrupts | — | 3.11.2 on page 182 |
| DMB | — | Data memory barrier | — | 3.11.4 on page 184 |
| DSB | — | Data synchronization barrier | — | 3.11.4 on page 184 |
| EOR, EORS | {Rd,} Rn, Op2 | Exclusive OR | N,Z,C | 3.5.2 on page 85 |
| ISB | — | Instruction synchronization barrier | — | 3.11.5 on page 185 |
| IT | — | If-then condition block | — | 3.9.7 on page 145 |
| LDM | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
| LDMDB, LDMEA | Rn{!}, reglist | Load multiple registers, decrement before | — | 3.4.6 on page 76 |
| LDMFD, LDMIA | Rn{!}, reglist | Load multiple registers, increment after | — | 3.4.6 on page 76 |
| LDR | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
| LDRB, LDRBT | Rt, [Rn, #offset] | Load register with byte | — | 3.4 on page 69 |
| LDRD | Rt, Rt2, [Rn, #offset] | Load register with two bytes | — | 3.4.2 on page 71 |
| LDREX | Rt, [Rn, #offset] | Load register exclusive | — | 3.4.8 on page 79 |
> 原始图片：imgs/page_51_*.png（无图则注明无图）
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来源：PM0214 Rev 10，Page 52
# The STM32 Cortex-M4 instruction set
**Table 21. Cortex-M4 instructions (continued)**
| Mnemonic | Operands | Brief description | Flags | Page |
|----------|----------|-------------------|-------|------|
| LDREXB | Rt, [Rn] | Load register exclusive with byte | — | 3.4.8 on page 79 |
| LDREXH | Rt, [Rn] | Load register exclusive with halfword | — | 3.4.8 on page 79 |
| LDRH, LDRHT | Rt, [Rn, #offset] | Load register with halfword | — | 3.4 on page 69 |
| LDRSB, LDRSBT | Rt, [Rn, #offset] | Load register with signed byte | — | 3.4 on page 69 |
| LDRSH, LDRSHT | Rt, [Rn, #offset] | Load register with signed halfword | — | 3.4 on page 69 |
| LDRT | Rt, [Rn, #offset] | Load register with word | — | 3.4 on page 69 |
| LSL, LSLS | Rd, Rm, <Rs\|#n> | Logical shift left | N,Z,C | 3.5.3 on page 86 |
| LSR, LSRS | Rd, Rm, <Rs\|#n> | Logical shift right | N,Z,C | 3.5.3 on page 86 |
| MLA | Rd, Rn, Rm, Ra | Multiply with accumulate, 32-bit result | — | 3.6.1 on page 110 |
| MLS | Rd, Rn, Rm, Ra | Multiply and subtract, 32-bit result | — | 3.6.1 on page 110 |
| MOV, MOVS | Rd, Op2 | Move | N,Z,C | 3.5.6 on page 89 |
| MOVT | Rd, #imm16 | Move top | — | 3.5.7 on page 91 |
| MOVW, MOV | Rd, #imm16 | Move 16-bit constant | N,Z,C | 3.5.6 on page 89 |
| MRS | Rd, spec_reg | Move from special register to general register | — | 3.11.6 on page 186 |
| MSR | spec_reg, Rm | Move from general register to special register | N,Z,C,V | 3.11.7 on page 187 |
| MUL, MULS | {Rd,} Rn, Rm | Multiply, 32-bit result | N,Z | 3.6.1 on page 110 |
| MVN, MVNS | Rd, Op2 | Move NOT | N,Z,C | 3.5.6 on page 89 |
| NOP | — | No operation | — | 3.11.8 on page 188 |
| ORN, ORNS | {Rd,} Rn, Op2 | Logical OR NOT | N,Z,C | 3.5.2 on page 85 |
| ORR, ORRS | {Rd,} Rn, Op2 | Logical OR | N,Z,C | 3.5.2 on page 85 |
| PKHTB, PKHBT | {Rd,} Rn, Rm, Op2 | Pack Halfword | — | 3.8.1 on page 135 |
| POP | reglist | Pop registers from stack | — | 3.4.7 on page 78 |
| PUSH | reglist | Push registers onto stack | — | 3.4.7 on page 78 |
| QADD | {Rd,} Rn, Rm | Saturating double and add | — | 3.7.3 on page 128 |
| QADD16 | {Rd,} Rn, Rm | Saturating add 16 | — | 3.7.3 on page 128 |
| QADD8 | {Rd,} Rn, Rm | Saturating add 8 | — | 3.7.3 on page 128 |
| QASX | {Rd,} Rn, Rm | Saturating add and subtract with exchange | — | 3.7.4 on page 129 |
> 原始图片：imgs/page_52_*.png（无图则注明无图）
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封面截图待提取