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2.1.4_Exceptions_and_interrupts_p20.md

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+来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 20
+
+These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignment is
+shown in Figure 3 and Figure 4.
+
+**Figure 3. APSR, IPSR and EPSR bit assignment**
+
+![图 3](imgs/page_20_fig_3.png)
+
+**Figure 4. PSR bit assignment**
+
+![图 4](imgs/page_20_fig_4.png)
+
+Access these registers individually or as a combination of any two or all three registers,
+using the register name as an argument to the MSR or MRS instructions. For example:
+- Read all of the registers using PSR with the MRS instruction.
+- Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.
+The PSR combinations and attributes are:
+
+See the instruction descriptions MRS on page 186 and MSR on page 187 for more
+information about how to access the program status registers.
+
+**Table 4. PSR register combinations**
+
+| Register | Type | Combination |
+|----------|------|-------------|
+| PSR | read-write(1), (2) | APSR, EPSR, and IPSR |
+| IEPSR | read-only | EPSR and IPSR |
+| IAPSR | read-write(1) | APSR and IPSR |
+| EAPSR | read-write(2) | APSR and EPSR |
+
+1. The processor ignores writes to the IPSR bits.
+2. Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
+
+|25 24 23 | Reserved | ISR_NUMBER | 31 30 29 28 27 | N Z C V | 0 | Reserved |
+|----------|----------|------------|----------------|---------|---|----------|
+| 26 | Reserved | | 16 15 | ICI/IT | ICI/IT | T | Q |
+| 8 | 19 | 20 | GE[3:0] | Reserved | | |
+
+> 原始图片：imgs/page_20_fig_3.png, imgs/page_20_fig_4.png