| 章节号 | 标题 | 页码 |
|--------|------|------|
| 1 | About this document | 12 |
| 1.1 | Typographical conventions | 12 |
| 1.2 | List of abbreviations for registers | 12 |
| 1.3 | About the STM32 Cortex-M4 processor and core peripherals | 13 |
| 1.3.1 | System level interface | 14 |
| 1.3.2 | Integrated configurable debug | 14 |
| 1.3.3 | Cortex-M4 processor features and benefits summary | 15 |
| 1.3.4 | Cortex-M4 core peripherals | 16 |
| 2 | The Cortex-M4 processor | 17 |
| 2.1 | Programmers model | 17 |
| 2.1.1 | Processor mode and privilege levels for software execution | 17 |
| 2.1.2 | Stacks | 17 |
| 2.1.3 | Core registers | 18 |
| 2.1.4 | Exceptions and interrupts | 26 |
| 2.1.5 | Data types | 26 |
| 2.1.6 | The Cortex microcontroller software interface standard (CMSIS) | 26 |
| 2.2 | Memory model | 28 |
| 2.2.1 | Memory regions, types and attributes | 29 |
| 2.2.2 | Memory system ordering of memory accesses | 29 |
| 2.2.3 | Behavior of memory accesses | 30 |
| 2.2.4 | Software ordering of memory accesses | 31 |
| 2.2.5 | Bit-banding | 32 |
| 2.2.6 | Memory endianness | 34 |
| 2.2.7 | Synchronization primitives | 34 |
| 2.2.8 | Programming hints for the synchronization primitives | 36 |
| 2.3 | Exception model | 37 |
| 2.3.1 | Exception states | 37 |
| 2.3.2 | Exception types | 37 |
| 2.3.3 | Exception handlers | 39 |
| 2.3.4 | Vector table | 40 |
| 2.3.5 | Exception priorities | 41 |
| 2.3.6 | Interrupt priority grouping | 41 |
| 2.3.7 | Exception entry and return | 42 |