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新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
61 lines
2.6 KiB
Plaintext
61 lines
2.6 KiB
Plaintext
PM0214 Rev 10
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197/262
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PM0214
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Core peripherals
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261
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; R3 = attributes
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; R4 = address
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LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
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STR R1, [R0, #0x0] ; Region Number
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BIC R2, R2, #1 ; Disable
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STRH R2, [R0, #0x8] ; Region Size and Enable
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STR R4, [R0, #0x4] ; Region Base Address
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STRH R3, [R0, #0xA] ; Region Attribute
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ORR R2, #1 ; Enable
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STRH R2, [R0, #0x8] ; Region Size and Enable
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Software must use memory barrier instructions:
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•
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Before MPU setup if there might be outstanding memory transfers, such as buffered
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writes, that might be affected by the change in MPU settings
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•
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After MPU setup if it includes memory transfers that must use the new MPU settings.
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However, memory barrier instructions are not required if the MPU setup process starts by
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entering an exception handler, or is followed by an exception return, because the exception
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entry and exception return mechanism cause memory barrier behavior.
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Software does not need any memory barrier instructions during MPU setup, because it
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accesses the MPU through the PPB, which is a Strongly-Ordered memory region.
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For example, if you want all of the memory access behavior to take effect immediately after
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the programming sequence, use a DSB instruction and an ISB instruction:
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•
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A DSB is required after changing MPU settings, such as at the end of context switch.
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•
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An ISB is required if the code that programs the MPU region or regions is entered using
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a branch or call. If the programming sequence is entered using a return from exception,
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or by taking an exception, then you do not require an ISB.
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Updating an MPU region using multi-word writes
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You can program directly using multi-word writes, depending on how the information is
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divided. Consider the following reprogramming:
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; R1 = region number
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; R2 = address
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; R3 = size, attributes in one
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LDR R0, =MPU_RNR
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; 0xE000ED98, MPU region number register
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STR R1, [R0, #0x0]
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; Region Number
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STR R2, [R0, #0x4]
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; Region Base Address
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STR R3, [R0, #0x8]
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; Region Attribute, Size and Enable
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Use an STM instruction to optimize this:
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; R1 = region number
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; R2 = address
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; R3 = size, attributes in one
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LDR R0, =MPU_RNR
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; 0xE000ED98, MPU region number register
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STM R0, {R1-R3}
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; Region Number, address, attribute, size and enable
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You can do this in two words for pre-packed information. This means that the RBAR
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contains the required region number and had the VALID bit set to 1, see MPU region base
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address register (MPU_RBAR) on page 203. Use this when the data is statically packed, for
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example in a boot loader:
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