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新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
40 lines
1.6 KiB
Markdown
40 lines
1.6 KiB
Markdown
来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 2
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| 章节号 | 标题 | 页码 |
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|--------|------|------|
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| 1 | About this document | 12 |
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| 1.1 | Typographical conventions | 12 |
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| 1.2 | List of abbreviations for registers | 12 |
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| 1.3 | About the STM32 Cortex-M4 processor and core peripherals | 13 |
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| 1.3.1 | System level interface | 14 |
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| 1.3.2 | Integrated configurable debug | 14 |
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| 1.3.3 | Cortex-M4 processor features and benefits summary | 15 |
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| 1.3.4 | Cortex-M4 core peripherals | 16 |
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| 2 | The Cortex-M4 processor | 17 |
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| 2.1 | Programmers model | 17 |
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| 2.1.1 | Processor mode and privilege levels for software execution | 17 |
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| 2.1.2 | Stacks | 17 |
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| 2.1.3 | Core registers | 18 |
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| 2.1.4 | Exceptions and interrupts | 26 |
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| 2.1.5 | Data types | 26 |
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| 2.1.6 | The Cortex microcontroller software interface standard (CMSIS) | 26 |
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| 2.2 | Memory model | 28 |
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| 2.2.1 | Memory regions, types and attributes | 29 |
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| 2.2.2 | Memory system ordering of memory accesses | 29 |
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| 2.2.3 | Behavior of memory accesses | 30 |
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| 2.2.4 | Software ordering of memory accesses | 31 |
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| 2.2.5 | Bit-banding | 32 |
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| 2.2.6 | Memory endianness | 34 |
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| 2.2.7 | Synchronization primitives | 34 |
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| 2.2.8 | Programming hints for the synchronization primitives | 36 |
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| 2.3 | Exception model | 37 |
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| 2.3.1 | Exception states | 37 |
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| 2.3.2 | Exception types | 37 |
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| 2.3.3 | Exception handlers | 39 |
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| 2.3.4 | Vector table | 40 |
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| 2.3.5 | Exception priorities | 41 |
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| 2.3.6 | Interrupt priority grouping | 41 |
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| 2.3.7 | Exception entry and return | 42 |
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> 原始图片：imgs/page_2_*.png（无图则注明无图）
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