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新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述) 原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表 Co-Authored-By: Claude <noreply@anthropic.com>
44 lines
2.5 KiB
Markdown
44 lines
2.5 KiB
Markdown
来源：STM32 Cortex®-M4 MCUs and MPUs Programming Manual Rev 10，Page 238
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4.4.11
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Usage fault status register (UFSR)
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Bits 31:26 Reserved, must be kept cleared
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Bit 25 DIVBYZERO: Divide by zero usage fault. When the processor sets this bit to 1, the PC value
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stacked for the exception return points to the instruction that performed the divide by zero.
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Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see
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Configuration and control register (CCR) on page 231.
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0: No divide by zero fault, or divide by zero trapping not enabled
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1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
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Bit 24 UNALIGNED: Unaligned access usage fault. Enable trapping of unaligned accesses by
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setting the UNALIGN_TRP bit in the CCR to 1, see Configuration and control register (CCR)
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on page 231.
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Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
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UNALIGN_TRP.
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0: No unaligned access fault, or unaligned access trapping not enabled
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1: the processor has made an unaligned memory access.
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Bits 23:20 Reserved, must be kept cleared
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Bit 19 NOCP: No coprocessor usage fault. The processor does not support coprocessor instructions:
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0: No usage fault caused by attempting to access a coprocessor
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1: the processor has attempted to access a coprocessor.
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Bit 18 INVPC: Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN:
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When this bit is set to 1, the PC value stacked for the exception return points to the instruction
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that tried to perform the illegal load of the PC.
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0: No invalid PC load usage fault
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1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an
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invalid context, or an invalid EXC_RETURN value.
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Bit 17 INVSTATE: Invalid state usage fault. When this bit is set to 1, the PC value stacked for
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the exception return points to the instruction that attempted the illegal use of the EPSR.
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This bit is not set to 1 if an undefined instruction uses the EPSR.
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0: No invalid state usage fault
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1: The processor has attempted to execute an instruction that makes illegal use of the
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EPSR.
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Bit 16 UNDEFINSTR: Undefined instruction usage fault. When this bit is set to 1, the PC value
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stacked for the exception return points to the undefined instruction.
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An undefined instruction is an instruction that the processor cannot decode.
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0: No undefined instruction usage fault
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1: The processor has attempted to execute an undefined instruction.
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Bits 15:0 Reserved, must be kept cleared
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> 原始图片：imgs/page_238_*.png（无图则注明无图）
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