68 lines
2.4 KiB
Markdown
68 lines
2.4 KiB
Markdown
# 4.4.10 Configurable fault status register (CFSR; UFSR+BFSR+MMFSR)
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**Address offset:** `0x28`
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**Reset value:** `0x0000 0000`
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**Required privilege:** Privileged
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The CFSR is byte-accessible and indicates the cause of a memory management fault, bus fault, or usage fault.
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## CFSR subregisters
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| Subregister | Address | Access |
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|-------------|----------|--------|
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| MMFSR | Bits[7:0] | Byte access at `0xE000ED28` |
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| BFSR | Bits[15:8] | Byte access at `0xE000ED29` |
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| UFSR | Bits[31:16] | Halfword access at `0xE000ED2A` |
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| Full CFSR | Bits[31:0] | Word access at `0xE000ED28` |
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## Bitfield definitions
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### UFSR — Usage Fault Status Register (Bits[31:16])
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| Bit | Field | Type | Description |
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|-----|-------|------|-------------|
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| 31 | DIVBY | rc_w1 | Divide by zero trap |
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| 30 | ZERO | rc_w1 | Unaligned memory access trap |
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| 29 | UNALI | rc_w1 | Unaligned access fault |
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| 28 | UNALIGNED | rc_w1 | Unaligned memory access fault |
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| 27 | Reserved | - | - |
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| 26 | NOCP | rc_w1 | No coprocessor fault |
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| 25 | INVPC | rc_w1 | Invalid PC load fault |
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| 24 | INVSTATE | rc_w1 | Invalid state fault |
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| 23 | UNDEF | rc_w1 | Undefined instruction fault |
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| 22 | Reserved | - | - |
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| 21 | INSTR | rc_w1 | Instruction access fault |
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### BFSR — Bus Fault Status Register (Bits[15:8])
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| Bit | Field | Type | Description |
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|-----|-------|------|-------------|
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| 15 | BFARVALID | rc_w1 | Bus Fault Address Register valid |
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| 14 | Reserved | - | - |
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| 13 | LSPERR | rw | Lazy save error |
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| 12 | STKERR | rw | Stack error |
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| 11 | UNSTKERR | rw | Unstack error |
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| 10 | IMPRECISERR | rw | Imprecise data access error |
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| 9 | PRECISERR | rw | Precise data access error |
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| 8 | IBUSERR | rw | Instruction bus error |
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### MMFSR — Memory Management Fault Status Register (Bits[7:0])
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| Bit | Field | Type | Description |
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|-----|-------|------|-------------|
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| 7 | MMARVALID | rc_w1 | Memory Management Fault Address Register valid |
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| 6 | Reserved | - | - |
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| 5 | MLSPERR | rw | Lazy save error (memory management) |
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| 4 | MSTKERR | rw | Stack error (memory management) |
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| 3 | MUNSTKERR | rw | Unstack error (memory management) |
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| 2 | Reserved | - | - |
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| 1 | DACCVIOL | rw | Data access violation |
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| 0 | IACCVIOL | rw | Instruction access violation |
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---
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## See also
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- Usage fault status register (UFSR) — page 238
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- Bus fault status register (BFSR) — page 239
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- Memory management fault address register (MMFSR) — page 240 |