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test: PDF洗MD v5 第二批测试 — 12页（含寄存器/代码/位域表）

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新增6页：p18(寄存器+Table)/p20-p21(PSR双图+APSR位域)/p197(MPU汇编)/p237-238(CFSR/UFSR位域描述)
原有6页：p1封面/p2目录/p12-p13正文/p51-p52指令表

Co-Authored-By: Claude <noreply@anthropic.com>
This commit is contained in:
hwd32
2026-06-10 16:03:04 +08:00
parent e594216bfa
commit a0549647dc
24 changed files with 1199 additions and 42 deletions
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source/page_1.txt
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@@ -45,4 +45,4 @@ STM32L4+ Series, STM32WB Series, STM32WL Series
STM32H745/755 and STM32H747/757 Lines
Microprocessors
STM32MP1 Series
www.st.com
www.st.com
source/page_12.txt
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@@ -20,7 +20,7 @@ The following abbreviations are used in register descriptions:
a.
Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
italic
Highlights important notes, introduces special terminology, denotes
Highlights important notes, introduces special terminology, denotes
internal cross-references, and citations.
< and >
Enclose replaceable terms for assembler syntax where they appear in
@@ -44,4 +44,4 @@ read-only (r)
Software can only read these bits.
write-only (w)
Software can only write to this bit.
Reading the bit returns the reset value.
Reading the bit returns the reset value.
source/page_13.txt
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@@ -27,12 +27,12 @@ hardware division.
Figure 1. STM32 Cortex-M4 implementation
read/clear (rc_w1)
Software can read as well as clear this bit by writing 1.
Writing '0' has no effect on the bit value.
Writing ‘0’ has no effect on the bit value.
read/clear (rc_w0)
Software can read as well as clear this bit by writing 0.
Writing '1' has no effect on the bit value.
Writing ‘1’ has no effect on the bit value.
toggle (t)
Software can only toggle this bit by writing '1'. Writing '0' has no effect.
Software can only toggle this bit by writing ‘1’. Writing ‘0’ has no effect.
Reserved (Res.)
Reserved bit, must be kept at reset value.
Embedded
@@ -59,4 +59,4 @@ Cortex-M4
processor
FPU
Processor
core
core
source/page_18.txt
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The Cortex-M4 processor
PM0214
18/262
PM0214 Rev 10
2.1.3
Core registers
Figure 2. Processor core registers
Table 2. Summary of processor mode, execution privilege level, and stack usage
Processor
mode
Used to
execute
Privilege level for
software execution
Stack used
Thread
Applications
Privileged or unprivileged (1)
1.
See CONTROL register on page 25.
Main stack or process stack (1)
Handler
Exception handlers
Always privileged
Main stack
Table 3. Core register set summary
Name
Type (1)
Required
privilege (2)
Reset
value
Description
R0-R12
read-write
Either
Unknown
General-purpose registers on page 19
MSP
read-write
Privileged
See description Stack pointer on page 19
PSP
read-write
Either
Unknown
Stack pointer on page 19
LR
read-write
Either
0xFFFFFFFF
Link register on page 19
PC
read-write
Either
See description Program counter on page 19
source/page_197.txt
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PM0214 Rev 10
197/262
PM0214
Core peripherals
261
; R3 = attributes
; R4 = address
LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0] ; Region Number
BIC R2, R2, #1 ; Disable
STRH R2, [R0, #0x8] ; Region Size and Enable
STR R4, [R0, #0x4] ; Region Base Address
STRH R3, [R0, #0xA] ; Region Attribute
ORR R2, #1 ; Enable
STRH R2, [R0, #0x8] ; Region Size and Enable
Software must use memory barrier instructions:
•
Before MPU setup if there might be outstanding memory transfers, such as buffered
writes, that might be affected by the change in MPU settings
•
After MPU setup if it includes memory transfers that must use the new MPU settings.
However, memory barrier instructions are not required if the MPU setup process starts by
entering an exception handler, or is followed by an exception return, because the exception
entry and exception return mechanism cause memory barrier behavior.
Software does not need any memory barrier instructions during MPU setup, because it
accesses the MPU through the PPB, which is a Strongly-Ordered memory region.
For example, if you want all of the memory access behavior to take effect immediately after
the programming sequence, use a DSB instruction and an ISB instruction:
•
A DSB is required after changing MPU settings, such as at the end of context switch.
•
An ISB is required if the code that programs the MPU region or regions is entered using
a branch or call. If the programming sequence is entered using a return from exception,
or by taking an exception, then you do not require an ISB.
Updating an MPU region using multi-word writes
You can program directly using multi-word writes, depending on how the information is
divided. Consider the following reprogramming:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
; 0xE000ED98, MPU region number register
STR R1, [R0, #0x0]
; Region Number
STR R2, [R0, #0x4]
; Region Base Address
STR R3, [R0, #0x8]
; Region Attribute, Size and Enable
Use an STM instruction to optimize this:
; R1 = region number
; R2 = address
; R3 = size, attributes in one
LDR R0, =MPU_RNR
; 0xE000ED98, MPU region number register
STM R0, {R1-R3}
; Region Number, address, attribute, size and enable
You can do this in two words for pre-packed information. This means that the RBAR
contains the required region number and had the VALID bit set to 1, see MPU region base
address register (MPU_RBAR) on page 203. Use this when the data is statically packed, for
example in a boot loader:
source/page_2.txt
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@@ -4,68 +4,68 @@ PM0214
PM0214 Rev 10
Contents
1
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
About this document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1
Typographical conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typographical conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3
About the STM32 Cortex-M4 processor and core peripherals . . . . . . . . . . 13
About the STM32 Cortex-M4 processor and core peripherals . . . . . . . . . 13
1.3.1
System level interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
System level interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.2
Integrated configurable debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Integrated configurable debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.3
Cortex-M4 processor features and benefits summary . . . . . . . . . . . . . 15
Cortex-M4 processor features and benefits summary . . . . . . . . . . . . . . 15
1.3.4
Cortex-M4 core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Cortex-M4 core peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2
The Cortex-M4 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
The Cortex-M4 processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1
Programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Programmers model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.1
Processor mode and privilege levels for software execution . . . . . . . . 17
Processor mode and privilege levels for software execution . . . . . . . . . 17
2.1.2
Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.1.3
Core registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Core registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.4
Exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Exceptions and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1.5
Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.1.6
The Cortex microcontroller software interface standard (CMSIS) . . . 26
The Cortex microcontroller software interface standard (CMSIS) . . . . . 26
2.2
Memory model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Memory model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.1
Memory regions, types and attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory regions, types and attributes . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.2
Memory system ordering of memory accesses . . . . . . . . . . . . . . . . . . 29
Memory system ordering of memory accesses . . . . . . . . . . . . . . . . . . . 29
2.2.3
Behavior of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Behavior of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.4
Software ordering of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . . 31
Software ordering of memory accesses . . . . . . . . . . . . . . . . . . . . . . . . 31
2.2.5
Bit-banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Bit-banding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.2.6
Memory endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Memory endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.7
Synchronization primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Synchronization primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2.8
Programming hints for the synchronization primitives . . . . . . . . . . . . . . 36
Programming hints for the synchronization primitives . . . . . . . . . . . . . . 36
2.3
Exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Exception model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.1
Exception states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Exception states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.2
Exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Exception types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.3.3
Exception handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Exception handlers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.3.4
Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.3.5
Exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Exception priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3.6
Interrupt priority grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interrupt priority grouping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.3.7
Exception entry and return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Exception entry and return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
source/page_20.txt
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The Cortex-M4 processor
PM0214
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These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignment is
shown in Figure 3 and Figure 4.
Figure 3. APSR, IPSR and EPSR bit assignment
Figure 4. PSR bit assignment
Access these registers individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example:
•
Read all of the registers using PSR with the MRS instruction.
•
Write to the APSR N, Z, C, V, and Q bits using APSR_nzcvq with the MSR instruction.
The PSR combinations and attributes are:
See the instruction descriptions MRS on page 186 and MSR on page 187 for more
information about how to access the program status registers.
Table 4. PSR register combinations
Register
Type
Combination
PSR
read-write(1), (2)
1.
The processor ignores writes to the IPSR bits.
2.
Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
APSR, EPSR, and IPSR
IEPSR
read-only
EPSR and IPSR
IAPSR
read-write(1)
APSR and IPSR
EAPSR
read-write(2)
APSR and EPSR
25 24 23
Reserved
ISR_NUMBER
31 30 29 28 27
N Z C V
0
Reserved
APSR
IPSR
EPSR
Reserved
Reserved
26
16 15
10 9
Reserved
ICI/IT
ICI/IT
T
Q
8
19
20
GE[3:0]
Reserved
25 24 23
31 30 29 28 27
N Z C V
0
PSR
Reserved
26
16 15
10 9
ICI/IT
Q
8
19
20
GE[3:0]
Reserved
ISR_NUMBER
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PM0214 Rev 10
21/262
PM0214
The Cortex-M4 processor
261
Application program status register
The APSR contains the current state of the condition flags from previous instruction
executions. See the register summary in Table 3 on page 18 for its attributes. The bit
assignment is:
Table 5. APSR bit definitions
Bits
Description
Bit 31
N: Negative or less than flag:
0: Operation result was positive, zero, greater than, or equal
1: Operation result was negative or less than.
Bit 30
Z: Zero flag:
0: Operation result was not zero
1: Operation result was zero.
Bit 29
C: Carry or borrow flag:
0: Add operation did not result in a carry bit or subtract operation resulted in a
borrow bit
1: Add operation resulted in a carry bit or subtract operation did not result in a
borrow bit.
Bit 28
V: Overflow flag:
0: Operation did not result in an overflow
1: Operation resulted in an overflow.
Bit 27
Q: DSP overflow and saturation flag: Sticky saturation flag.
0: Indicates that saturation has not occurred since reset or since the bit was last
cleared to zero
1: Indicates when an SSAT or USAT instruction results in saturation, or indicates a
DSP overflow.
This bit is cleared to zero by software using an MRS instruction.
Bits 26:20
Reserved.
Bits 19:16
GE[3:0]: Greater than or Equal flags. See SEL on page 105 for more information.
Bits 15:0
Reserved.
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PM0214 Rev 10
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Core peripherals
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4.4.10
Configurable fault status register (CFSR; UFSR+BFSR+MMFSR)
Address offset: 0x28
Reset value: 0x0000 0000
Required privilege: Privileged
The following subsections describe the subregisters that make up the CFSR:
•
Usage fault status register (UFSR) on page 238
•
Bus fault status register (BFSR) on page 239
•
Memory management fault address register (MMFSR) on page 240
The CFSR is byte accessible. You can access the CFSR or its subregisters as follows:
•
Access the complete CFSR with a word access to 0xE000ED28
•
Access the MMFSR with a byte access to 0xE000ED28
•
Access the MMFSR and BFSR with a halfword access to 0xE000ED28
•
Access the BFSR with a byte access to 0xE000ED29
•
Access the UFSR with a halfword access to 0xE000ED2A.
The CFSR indicates the cause of a memory management fault, bus fault, or usage fault.
Figure 20. CFSR subregisters
Memory Management
Fault Status Register
31
16 15
8
7
0
Usage Fault Status Register
Bus Fault Status
Register
UFSR
BFSR
MMFSR
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
DIVBY
ZERO
UNALI
GNED
Reserved
NOCP
INVPC
INV
STATE
UNDEF
INSTR
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
rc_w1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BFARV
ALID
Reserv
ed
LSP
ERR
STK
ERR
UNSTK
ERR
IMPRE
CIS
ERR
PRECI
S ERR
IBUS
ERR
MMAR
VALID
Reserv
ed
MLSP
ERR
MSTK
ERR
M
UNSTK
ERR
Res.
DACC
VIOL
IACC
VIOL
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 31:16 UFSR: see Usage fault status register (UFSR) on page 238
Bits 15:8 BFSR: see Bus fault status register (BFSR) on page 239
Bits 7:0 MMFSR: see Memory management fault address register (MMFSR) on page 240
source/page_238.txt
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Core peripherals
PM0214
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PM0214 Rev 10
4.4.11
Usage fault status register (UFSR)
Bits 31:26 Reserved, must be kept cleared
Bit 25 DIVBYZERO: Divide by zero usage fault. When the processor sets this bit to 1, the PC value
stacked for the exception return points to the instruction that performed the divide by zero.
Enable trapping of divide by zero by setting the DIV_0_TRP bit in the CCR to 1, see
Configuration and control register (CCR) on page 231.
0: No divide by zero fault, or divide by zero trapping not enabled
1: The processor has executed an SDIV or UDIV instruction with a divisor of 0.
Bit 24 UNALIGNED: Unaligned access usage fault. Enable trapping of unaligned accesses by
setting the UNALIGN_TRP bit in the CCR to 1, see Configuration and control register (CCR)
on page 231.
Unaligned LDM, STM, LDRD, and STRD instructions always fault irrespective of the setting of
UNALIGN_TRP.
0: No unaligned access fault, or unaligned access trapping not enabled
1: the processor has made an unaligned memory access.
Bits 23:20 Reserved, must be kept cleared
Bit 19 NOCP: No coprocessor usage fault. The processor does not support coprocessor instructions:
0: No usage fault caused by attempting to access a coprocessor
1: the processor has attempted to access a coprocessor.
Bit 18 INVPC: Invalid PC load usage fault, caused by an invalid PC load by EXC_RETURN:
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that tried to perform the illegal load of the PC.
0: No invalid PC load usage fault
1: The processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an
invalid context, or an invalid EXC_RETURN value.
Bit 17 INVSTATE: Invalid state usage fault. When this bit is set to 1, the PC value stacked for the
exception return points to the instruction that attempted the illegal use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
0: No invalid state usage fault
1: The processor has attempted to execute an instruction that makes illegal use of the
EPSR.
Bit 16 UNDEFINSTR: Undefined instruction usage fault. When this bit is set to 1, the PC value
stacked for the exception return points to the undefined instruction.
An undefined instruction is an instruction that the processor cannot decode.
0: No undefined instruction usage fault
1: The processor has attempted to execute an undefined instruction.
source/page_51.txt
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Operands
Brief description
Flags
Page
Page
source/page_52.txt
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Operands
Brief description
Flags
Page
Page